View EM73362_8990204.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product general description general description general description general description general description EM73362 is an advanced single chip cmos 4-bit micro-controller. it contains 3k-byte rom, 52-nibble ram, 4-bit alu, 13-level subroutine nesting, 22-stage time base, one 12-bit timer for the kernal function and one high speed counter. EM73362 also contains 5 interrupt sources, 1 input port, 4 bidirection ports, built-in watch- dog-timer and lcd driver (27x3 to 15x3). except low-power consumption and high speed, EM73362 has the stop mode and idle mode operation for power saving function. features features features features features ? operation voltage : 1.2v to 1.8v.(clock frequency : 32 k hz) clock source : single clock system for crystal, connect a external resistor or external clock source, available by mask option. instruction set : 109 powerful instructions. instruction cycle time : up to 122s for 32 k hz. rom capacity : 3072 x 8 bits. ram capacity : 52 x 4 bits. input port : 1 port (4-bit). bidirection port : 4 ports (p4, p6, p7, p8) are available by mask option. p4 is a high current port. (p4.0 and tone available by mask option. p4.1~p4.3 are shared with the input/ output of rfo.) p6, p7 and p8 are shared with seg15-seg26. 12-bit timer : one 12-bit timer is programmable for timer. high speed counter : the high speed counter includes one 8-bit high speed counter, one 12-bit general counter and a resistor frequency oscillator. it has resistor to frequency oscillation mode, melody mode and auto load timer mode. built-in time base counter: 22 stages. subrountine nesting : up to 13 levels. interrupt : external interrupt . . . . . . 2 input interrupt sources. internal interrupt . . . . . . 2 timer overflow interrupts, 1 time base interrupt. lcd driver : 27x3 to 15x3 dots available by mask option. 1/3, 1/2 and static three kinds of duty (1/2 bias) selectable. the programming method of lcd driver is ram mapping. built-in watch-dog-timer is available by mask option. built-in low battery detector. power saving function : stop mode and idle mode. package type : chip form 49 pins.
2 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product function block diagram function block diagram function block diagram function block diagram function block diagram interrupt control time base 12-bit timer (ta) system control instruction decoder instruction register rom pc data bus reset control frequency doubler timing generator sleep mode control data pointer acc alu flag zc s g stack pointer stack ram hr lr i/o control p0.0(int1)/wakeup0 p0.1/wakeup1 p0.2(int0)/wakeup2 p0.3/wakeup3 reset clock generator xin xout lcd driver tone generator high speed counter va vb vee com0~com2 seg0~seg14 p4.0(rx)/tone p4.1(cs) tone p6,p7,p8/seg(26..15) wdt p4.2(ry) p4.3(rz) low battery detector bat
3 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product pin descriptions pin descriptions pin descriptions pin descriptions pin descriptions pin name function p in type vdd power supply (+) vss power supply (-) reset system reset input signal, low active reset_a mask option : none pull-up xin crystal / external resistor or external clock source osc_a / osc_f connecting pin xout crystal / external resistor connecting pin osc_a / osc_f p0.0(int1)/wakeup0, 2-bit input pins with external interrupt sources input input_j p0.2(int0)/wakeup2 and stop/idle releasing function mask option : wake-up enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none p0(1,3)/wakeup1,3 2-bit input pins with stop / idle releasing function input_h mask option : wakeup enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none p4.0(rx)/tone 1-bit bidirection i/o pin or inverse sound effect output or i/o_o rf oscillation mask option : tone enable, push-pull, high current pmos tone disable, open-drain(apply to rf oscillation) tone disable, push-pull, high current pmos tone disable, push-pull, low current pmos p4.1(cs) 1-bit bidirection i/o pin or rf oscillation bias pin i/o_x mask option : open-drain(apply to rf oscillation) push-pull, high current pmos push-pull, low current pmos p4.2(ry), p4.3(rz) 2-bit bidirection i/o pins or rf oscillation input pins i/o_y mask option : open-drain(apply to rf oscillation) push-pull, high current pmos push-pull, low current pmos p6(0..3)/seg(23..26), 12-bit bidirection i/o pins are shared with lcd segment pin i/o_o p7(0..3)/seg(19..22), mask option : segment enable, open-drain p8(0..3)/seg(15..18) segment disable, open-drain segment disable, push-pull, high current pmos segment disable, push-pull, low current pmos bat connect the capacitor for built-in low battery detector tone built-in tone generator output va, vb, vee connect the capacitors for lcd bias voltage com0 ~ com2 lcd common output pins seg0 ~ seg14 lcd segment output pins test tie vss as package type, no connecting as cob type.
4 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product ldax ldax ldax ldax ldax acc acc acc acc acc rom[dp] rom[dp] rom[dp] rom[dp] rom[dp] l l l l l ldaxi ldaxi ldaxi ldaxi ldaxi acc acc acc acc acc rom[dp] rom[dp] rom[dp] rom[dp] rom[dp] h h h h h ,dp+1 ,dp+1 ,dp+1 ,dp+1 ,dp+1 dp is a 12-bit data register which can store the program rom address to be the pointer for the rom code data. first, user load rom address into dp by instruction "stadpl, stadpm, stadph", then user can get the lower nibble of rom code data by instruction "ldax" and higher nibble by instruction "ldaxi". user's program and fixed data are stored in the program rom. user's program is according the pc value to send next executed instruction code. fixed data can be read out by table-look-up instruction. table-look-up instruction is depended on the data pointer (dp) to indicate to rom address, then to get the rom code data. function descriptions function descriptions function descriptions function descriptions function descriptions program rom ( 3k x 8 bits ) program rom ( 3k x 8 bits ) program rom ( 3k x 8 bits ) program rom ( 3k x 8 bits ) program rom ( 3k x 8 bits ) 3 k x 8 bits program rom contains user's program and some fixed data. the basic structure of program rom can be divided into 4 parts. 1. address 000h: reset start address. 2. address 002h - 00ch : 5 kinds of interrupt service routine entry addresses. 3. address 00eh-086h : scall subroutine entry address, only available at 00eh,016h,01eh,026h, 02eh, 036h, 03eh, 046h, 04eh, 056h, 05eh, 066h, 06eh, 076h, 07eh, 086h. 4. address 000h - 7ffh : lcall subroutine entry address. 5. address 000h - bffh : except used as above function, the other region can be used as user's program region. address 3072 x 8 bits 000h reset start address 002h int0; external interrupt service toutine entry address 004h 006h trga; timer/counter a interrupt service routine entry address 008h trgb; timer/counter b interrupt service routine entry address 00ah tbi; time base interrupt service routine entry address 00ch int1; external interrupt service routine entry address 00eh 086h bffh scall, subroutine call entry address . . .
5 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product stack: there are 13-level (maximum) stack for user using for subroutine (including interrupt and call). user can assign any level be the starting stack by giving the level number to stack pointer (sp). zero- page: from 00h to 0fh is the location of zero-page. it is used as the pointer in zero-page addressing mode for the instruction of "std #k,y; add #k,y; clr y,b; cmp k,y". program example: to wirte immediate data "07h" to address "03h" of ram and to clear bit 2 of ram. std #07h, 03h ; ram[03] 07h clr 0eh,2 ; ram[0eh] 2 0 increment address 20h - 2fh 30h - 33h level 0 level 4 level 8 level 12 level 1 level 5 level 9 level 2 level 6 level 10 level 3 level 7 level 11 increment 00h - 0fh 10h - 1fh stack zero-page data ram ( 52-nibble ) data ram ( 52-nibble ) data ram ( 52-nibble ) data ram ( 52-nibble ) data ram ( 52-nibble ) there is total 52 - nibble data ram from address 00 to 33h data ram includes 3 parts: zero page region, stacks and data area. program example: read out the rom code of address 777h by table-look-up instruction. ldia #07h; stadpl ; [dp] l 07h stadpm ; [dp] m 07h stadph ; [dp] h 07h, load dp=777h : ldl #00h; ldh #03h; ldax ; acc 6h stami ; ram[30] 6h ldaxi ; acc 5h stam ; ram[31] 5h ; org 777h data 56h; : when user using any instruction of call or subroutine, before entry the subroutine, the previous pc address will be saved into stack until return from those subroutines, the pc value will be restored by the data saved in stack. data area: except the special area used by user, the whole ram can be used as data area for storing and loading general data.
6 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product increment seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 program counter (3k rom) program counter (3k rom) program counter (3k rom) program counter (3k rom) program counter (3k rom) program counter ( pc ) is composed by a 12-bit counter, which indicates the next executed address for the instruction of program rom. for a 3k - byte size rom, pc can indicate address form 000h - bffh, for branch and call instructions, pc is changed by instruction indicating. (1) branch instruction: (1) branch instruction: (1) branch instruction: (1) branch instruction: (1) branch instruction: sbr a sbr a sbr a sbr a sbr a object code: 00aa aaaa condition: sf=1; pc pc 11-6.a ( branch condition satisified ) pc hold original pc value+1 aaaaaa sf=0; pc pc +1( branch condition not satisified) pc original pc value + 1 lbr a lbr a lbr a lbr a lbr a object code: 1100 aaaa aaaa aaaa condition: sf=1; pc a ( branch condition satisified) pcaaaaaaaaaaaa addressing mode (1) indirect addressing mode: indirect addressing mode indicates the ram address by specified hl register. for example: ldam ; acc ram[hl] stam ; ram[hl] acc (2) direct addressing mode: direct addressing mode indicates the ram address by immediate data. for example: lda x ; acc ram[x] sta x ; ram[x] acc (3) zero-page addressing mode for zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit manupulated operation directly. for example: std #k,y ; ram[y] #k add #k,y; ram[y] ram[y] + #k lcd displa lcd displa lcd displa lcd displa lcd displa y ram y ram y ram y ram y ram ram address from 40h ~ 46h, 50h ~ 56h, 60h ~ 66h are lcd display ram, the ram data of this region can't be operated by instruction ? ldhl xx ? and ? exhl ? . address increment bit 0 1 2 3 0 1 2 40h~46h (com0) 50h~56h (com1) 60h~66h (com2)
7 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product sf=0 ; pc pc + 2 (branch condition not satisfied) pc original pc value + 2 (2) subroutine instruction: (2) subroutine instruction: (2) subroutine instruction: (2) subroutine instruction: (2) subroutine instruction: scall a scall a scall a scall a scall a object code: 1110 nnnn condition : pc a ; a=8n+6 ; n=1..15 ; a=86h, n=0 lcall a lcall a lcall a lcall a lcall a object code: 0100 0aaa aaaa aaaa condition: pc a pc0aaaaaaaaaaa ret ret ret ret ret object code: 0100 1111 condition: pc stack[sp]; sp + 1 pc the return address stored in stack rt i rt i rt i rt i rt i object code: 0100 1101 condition : flag. pc stack[sp]; ei 1; sp + 1 pc the return address stored in stack (3) interrupt acceptance operation: (3) interrupt acceptance operation: (3) interrupt acceptance operation: (3) interrupt acceptance operation: (3) interrupt acceptance operation: when an interrupt is accepted, the original pc is pushed into stack and interrupt vector will be loaded into pc. the interrupt vectors are as following: int0 int0 int0 int0 int0 (external interrupt from p0.2) pc000000000010 trga trga trga trga trga (timer a overflow interrupt) pc000000000110 trgb trgb trgb trgb trgb (time b overflow interrupt) pc000000001000 tbi tbi tbi tbi tbi (time base interrupt) pc000000001010 pc 0 0 0 0 a a a a a a a a
8 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product int1 int1 int1 int1 int1 (external interrupt from p0.0) pc000000001100 (4) reset operation: (4) reset operation: (4) reset operation: (4) reset operation: (4) reset operation: pc000000000000 (5) other operations: (5) other operations: (5) other operations: (5) other operations: (5) other operations: for 1-byte instruction execution: pc + 1 for 2-byte instruction execution: pc + 2 there are four kinds of flag, cf (carry flag), zf (zero flag), sf (status flag) and gf (general flag), these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation. all flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after rti instruction executed. (1) carry flag ( cf ) the carry flag is affected by following operation : a. addition : cf as a carry out indicator, when the addition operation has a carry-out, cf will be "1", in another word, if the operation has no carry-out, cf will be "0". b. subtraction : cf as a borrow-in indicator, when the subtraction operation must has a borrow, in the cf will be "0", in another word, if no borrow-in, cf will be "1". c. comparision: cf is as a borrow-in indicator for comparision operation as the same as subtraction operation. d. rotation: cf shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. cf test instruction : for tfcfc instruction, the content of cf sends into sf then clear itself "0". for ttsfc instruction, the content of cf sends into sf then set itself "1". (2) zero flag ( zf ) zf is affected by the result of alu, if the alu operation generate a "0" result, the zf will be "1", otherwise, the zf will be "0". (3) status flag ( sf ) the sf is affected by instruction operation and system status. accumulator accumulator accumulator accumulator accumulator accumulator is a 4-bit data register for temporary data. for the arithematic, logic and comparative opertion .., acc plays a role which holds the source data and result. flags flags flags flags flags
9 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product alu alu alu alu alu the arithematic operation of 4 - bit data is performed in alu unit. there are 2 flags can be affected by the result of alu operation, zf and sf. the operation of alu can be affected by cf only. alu structure alu structure alu structure alu structure alu structure alu supported user arithematic operation function, including : addition, subtraction and rotaion. alu function alu function alu function alu function alu function (1) addition: for instruction addam, adcam, addm #k, add #k,y .... alu supports addition function. the addition operation can affect cf and zf. for addition operation, if the result is "0", zf will be "1", otherwise, not equal "0", zf will be "0". when the addition operation has a carry-out, cf will be "1", otherwise, cf will be "0". example: operation carry zero 3+4=7 0 0 7+f=6 1 0 0+0=0 0 1 8+8=0 1 1 (2) subtraction: for instruction subm #k, suba #k, sbcam, decm... alu supports user subtraction function. the subtraction operation can affect cf and zf, for subtraction operation, if the result is negative, cf will gf is a one bit general purpose register which can be set, clear, test by instruction sgf, cgf and tgs. program example : check following arithematic operation for cf, zf, sf cf zf sf ldia #00h; - 1 1 ldia #03h; - 0 1 adda #05h; - 0 1 adda #0dh; - 0 0 adda #0eh; - 0 0 a. sf is initiated to "1" for reset condition. b. branch instruction is decided by sf, when sf=1, branch condition will be satisified, otherwise, branch condition will not be satisified by sf = 0. (4) general flag ( gf ) zf cf sf gf alu data bus
10 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product acc cf msb lsb 3 2 1 0 h register 3 2 1 0 l register acc cf msb lsb (3) rotation: there are two kinds of rotation operation, one is rotation left, the other is rotation right. rlca instruction rotates acc value to left, shift the cf value into the lsb bit of acc and the shift out data will be hold in cf. rrca instruction operation rotates acc value to right, shift the cf value into the msb bit of acc and the shift out data will be hold in cf. program example: to rotate acc right and shift a "1" into the msb bit of acc. ttcfs; cf 1 rrca; rotate acc right and shift cf=1 into msb. hl register hl register hl register hl register hl register hl register are two 4-bit registers, they are used as a pair of pointer for the address of ram memory and also 2 independent temporary 4-bit data registers. for some instruction, l register can be a pointer to indicate the pin number (port4, port6, port7). hl register structure hl register structure hl register structure hl register structure hl register structure hl register function hl register function hl register function hl register function hl register function (1) for instruction : ldl #k, ldh #k, tha, thl, incl, decl, exal, exah, hl register used as a temporary register. program example: load immediate data "5h" into l register, "dh" into h register. ldl #05h; ldh #0dh; (2) for instruction ldam, stam, stami .., hl register used as a pointer for the address of ram memory. example: operation carry zero 8-4=4 1 0 7-f= -8(1000) 0 0 9-9=0 1 1 be "0", it means a borrow out, otherwise, if the result is positive, cf will be "1". for zf, if the result of subtraction operation is "0", the zf will be "1", otherwise, zf will be "1".
11 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product program example: store immediate data #ah into ram of address 35h. ldl #5h; ldh #3h; stdmi #0ah; ram[35] ah (3) for instruction : selp, clpl, tfpl, l register be a pointer to indicate the bit of i/o port. when lr = 0 - 1, indicate p4.0 - p4.1. program example: to set bit 1 of port 4 to "1" ldl #01h; sepl ; p4.1 1 stack pointer (sp) stack pointer (sp) stack pointer (sp) stack pointer (sp) stack pointer (sp) stack pointer is a 4-bit register which stores the present stack level number. before using stack, user must set the sp value first, cpu will not initiate the sp value after reset condition. when a new subroutine is accepted, the sp will be decreased one automatically, in another word, if returning from a subroutine, the sp will be increased one. the data transfer between acc and sp is by instruction of "ldasp" and "stasp". data pointer (dp) data pointer (dp) data pointer (dp) data pointer (dp) data pointer (dp) data pointer is a 12-bit register which stores the address of rom can indicate the rom code data specified by user (refer to data rom). clock and timing generator clock and timing generator clock and timing generator clock and timing generator clock and timing generator the clock generator is supported by a single clock system, the clock source comes from crystal (resonator) or rc oscillation, the working frequency range is 32 khz to 100 khz depending on the working voltage. clock and timing generator structure clock and timing generator structure clock and timing generator structure clock and timing generator structure clock and timing generator structure the clock generator connects outside compoments (crystal or resonator by xin and xout pin for crystal osc type, capacitor for rc osc type, these two type is decided by mask option) the clock generator generates a basic system clock "fc". when cpu sleeping, the clock generator will be stopped until the sleep condition released. the system clock control generates 4 basic phase signals (s1, s2, s3, s4) and system clock. sleep xout clock generator system clock control fc system clock s1 s2 s3 s4 mask option mask option for choose crystal or rc oscillation xin
12 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product idle mode normal operating mode stop mode reset operation command (p19) command (p16) reset reset reset reset release input pin or internal timer wakeup input timer wakeup xin xout crystal connection xin xout resistor connection clock and timing generator function clock and timing generator function clock and timing generator function clock and timing generator function clock and timing generator function the frequency of fc is the oscillation frequency for xin, xout by crystal (resonator) or by rc osc. when cpu sleeps, the xout pin will be in "high" state. the instruction cycle equal 4 basic clock fc. 1 instructure cycle = 4 / fc operation mode control operation mode control operation mode control operation mode control operation mode control EM73362 has 3 operation modes. they are normal, idle, and stop mode. operation mode oscillator cpu available function normal oscillating run lcd, rfc, low battery detector idle oscillating run lcd stop stop stop all disable
13 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product st st st st st op opera op opera op opera op opera op opera tion mode tion mode tion mode tion mode tion mode during stop operation mode, cpu holds the system ? s internal status with a low power consumption, for the stop mode, the system clock will be stopped in the stop condition and system need a warm up time for the stability of system clock running after wakeup. the stop operation mode is controlled by port 16 and released by p0(0..3)/ wakeup 0 3 .. . p16 3 2 1 0 initial value : 0000 spme swwt spme enable stop mode swwt set wake-up warm-up time 0 1 enable stop mode 0 0 2 9 / xin * * reserved 0 1 2 14 / xin 1 0 2 16 / xin 1 1 reserved stop operation mode condition : 1. osc stop and cpu internal status held. 2. internal time base clear to "0". 3. cpu internal memory, flags, register, i/o held original states. 4. program counter hold the executed address after stop release. release condition : 1. release stop operation mode by the falling edge of any one of p0(0..3)/ wakeup 0 3 .. . 2. osc start to oscillating. 3. warm-up time passing. 4. according pc to execute the following program. note : there are 4 independent mask options for wakeup function in EM73362. so, the wakeup function of p0(0..3)/ wakeup 0 3 .. are enabled or disabled independently. idle opera idle opera idle opera idle opera idle opera tion mode tion mode tion mode tion mode tion mode the idle operation mode retains the internal status with low power consumption without stopping the system clock function and lcd display. the idle operation mode is controlled by port 19 and released by p0(0..3)/ wakeup 0..3 or the internal timing generator. p19 3 2 1 0 initial value : 0000 idme sidr idme enable idle mode sidr select idle releasing condition 0 1 enable idle mode 0 0 p0(0..3) pin input * * reserved 0 1 p0(0..3) pin input and 1 sec signal 1 0 p0(0..3) pin input and 0.5 sec signal 1 1 p0(0..3) pin input and 15.625m sec signal
14 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product timing generator and time base timing generator and time base timing generator and time base timing generator and time base timing generator and time base the timing generator produces the system clock from basic clock pulse which can be normal mode or slow mode clock. 1 instruction cycle = 4 basic clock pulses there are 22 stages time base. when working in the single clock mode, the timebase clock source is come from fc. time base provides basic frequency for following function: 1. tbi (time base interrupt). 2. timer/counter, internal clock source. 3. warm-up time for stop - mode releasing. time base interrupt (tbi) time base interrupt (tbi) time base interrupt (tbi) time base interrupt (tbi) time base interrupt (tbi) the time base can be used to generate a fixed frequency interrupt. there are 8 kinds of frequencies can be selected by setting "p25" single clock mode p25 3 210( initial value 0000 ) 0 0 x x: interrupt disable 0 1 0 0: interrupt frequency xin / 2 9 hz 0 1 0 1: interrupt frequency xin / 2 10 hz 0 1 1 0: interrupt frequency xin / 2 12 hz 0 1 1 1: interrupt frequency xin / 2 13 hz 1 1 0 0: interrupt frequency xin / 2 14 hz 1 1 0 1: interrupt frequency xin / 2 15 hz 1 1 1 0: interrupt frequency xin / 2 16 hz 1 1 1 1: interrupt frequency xin / 2 17 hz 1 0 x x: reserved fc prescaler binary counter 12 3 0 5 6 7 8 9 10 11 12 13 421 20 19 18 17 16 15 14
15 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product timer control timer control timer control timer control timer control timer command port: p28 is the command port for timera. timer ( timera, timerb) timer ( timera, timerb) timer ( timera, timerb) timer ( timera, timerb) timer ( timera, timerb) EM73362 only can support timer function for timera. for timera, the timer data is saved in timer register tah, tam, tal, which user can set timer initial value and read the timer value by instruction "ldatah(m,l), statah(m,l)". this counter can be set initial value and send counter value to timer register, p28 is the command port for timera, user can choose different internal clock rate by setting this port. when timer overflows, it will generate a trga interrupt request to interrupt control unit. interrupt control timer control internal clock p28 12 bit counter tmsa ipsa data bus port 28 3 2 1 0 tmsa ipsa initial state: 0000 tmsa mode selection 0 0 stop 0 1 reserved 1 0 timer mode 1 1 reserved ipsa clock rate selection 0 0 xin/2 hz 0 1 xin/2 hz 1 0 xin/2 hz 1 1 xin/2 hz 5 7 11 15
16 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product timer function timer function timer function timer function timer function for timer mode, timera increase one at any rising edge of internal pulse. user can choose 4 kinds of internal pulse rate by setting ipsa for timera. when timera counts overflow, trga will be generated to interrupt control unit. program example: to generate trga interrupt request after 60 ms with system clock xln=32k hz ldia #0100b; exae; enable mask 2 eicil 110111b; interrupt latch 0, enable ei ldia #04h; statal; ldia #0ch; statam; ldia #0fh; statah; ldia #1000b; outa p28; enable timera with internal pulse rate: xin/2 5 hz note: the preset value of timer/counter register is calculated as following procedure. internal pulse rate: xin/2 5 ; xin = 32khz the time of timer counter count one = 2 5 /xin = 32/32k=1ms the number of internal pulse to get timer overflow = 60 ms/ 1ms = 60 = 03ch the preset value of timer/counter register = 1000h - 03ch = 0fc4h interrupt function interrupt function interrupt function interrupt function interrupt function there are 3 internal interrupt sources and 2 external interrupt sources. multiple interrupts are admitted according the priority. type type type type type interrupt source interrupt source interrupt source interrupt source interrupt source priority priority priority priority priority interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt program rom program rom program rom program rom program rom latch latch latch latch latch enable condition enable condition enable condition enable condition enable condition entry address entry address entry address entry address entry address external external interrupt (int0) 1 il5 ei=1 002h internal reserved 2 il4 ei=1, mask3=1 004h internal timera overflow interrupt (trga) 3 il3 ei=1, mask2=1 006h internal timerb overflow interrupt (trgb) 4 il2 ei=1, mask1=1 008h internal time base interrupt(tbi) 5 il1 00ah external external interrupt (int1) 6 il0 ei=1,mask0=1 00ch internal pulse timera value n n+1 n+2 n+3 n+4 n+5 n+6 n+7
17 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product interrupt structure interrupt structure interrupt structure interrupt structure interrupt structure interrupt controller: il0-il5 : interrupt latch. hold all interrupt requests from all interrupt sources. ilr can not be set by program, but can be reset by program or system reset, so il only can decide which interrupt source can be accepted. mask0-mask3 : mask register can promit or inhibit all interrupt sources. ei : enable interrupt flip-flop can promit or inhibit all interrupt sources, when inter- rupt happened, ei is cleared to "0" automatically, after rti instruction happened, ei will be set to "1" again. priority checker: check interrupt priority when multiple interrupts happened. interrupt function interrupt function interrupt function interrupt function interrupt function the procedure of interrupt operation: 1. push pc and all flags to stack. 2. set interrupt entry address into pc. 3. set sf= 1. 4. clear ei to inhibit other interrupts happened. 5. clear the il for which interrupt source has already be accepted. 6. to execute interrupt subroutine from the interrupt entry address. 7. cpu accept rti, restore pc and flags from stack. set ei to accept other interrupt requests. program example: to enable interrupt of "trga" ldia #1100b; exae; set mask register "1100b" eicil 111111b ; enable interrupt f.f. mask0 mask1 mask1 mask2 mask3 il0 r0 il1 tbi r1 reset by system reset and program instruction reserved il2 r2 il3 trga r3 il4 r4 il5 int0 r5 priority checker ei entry address generator interrupt request interrupt entry address reset by system reset and program instruction set by program instruction trgb int1
18 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product contr contr contr contr contr ol of lcd driver ol of lcd driver ol of lcd driver ol of lcd driver ol of lcd driver the lcd driver control command register is p27. when ldc is 00, the lcd is disabled and changes the duty only. when ldc is 01, the lcd is blanking, the com pins are inactive and the seg pins continuously output the display data. when ldc is 11, the lcd driver enables, the power switch is turned on and it cannot be turned off forever except the cpu is reseted or in the stop operation mode. users must enable the lcd driver by self when the cpu is woke up. p27 3 2 1 0 initial value : 0000 ldc duty ldc lcd display control duty driving method select 0 0 lcd display disable 0 0 reserved 0 1 blanking 0 1 1/3 duty ( 1/2 bias ) 1 0 reserved 1 0 1/2 duty ( 1/2 bias ) 1 1 lcd display enable 1 1 static lcd driving methods there are four kinds of driving methods can be selected by duty ( p27.0 ~ p27.1 ). the driving wave forms of lcd driver are as below : lcd driver lcd driver lcd driver lcd driver lcd driver EM73362 can directly drive the liquid crystal display (lcd) and has 27 segment, 3 common output pins. there are total 27 x 3 dots can be display. the vdd, vee, va, vb and vss pins are the bias voltage inputs of the lcd driver. the method of lcd programming is ram mapping. 1/3 duty (1/2 bias) seg0 seg0 - com0 on seg0 - com1 off frame com1 com2 com0 frame 1/2 duty (1/2 bias) m c o 2 o m c 1 c o m 0 seg0 seg1 seg2 : static on off frame
19 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product lcd frame frequency : according to the drive method to set the frame frequency. driving method frame frequency (hz) 1/3 duty 86 x (3/3) = 86 1/2 duty 86 x (3/2) = 129 static 86 lcd drive voltage when the power supply is 1.5v, the vee is connected a capacitor to vss and the va is connected a capacitor to vb for the voltage doubler. the output of vee is 2 x 1.5v for lcd bias voltage. va vb vee vdd vss 0.1uf 1.5v 0.1uf program example ldia #0001b ; set lcd mode 1/3 duty 1/2 bias outa p27 ldia #1100b outa p27 ; enable lcd : :
20 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product lcd displa lcd displa lcd displa lcd displa lcd displa y d y d y d y d y d a a a a a t t t t t a a a a a area area area area area the lcd display data is stored in ram from address 40h ~ 46h, 50h ~ 56h and 60h ~ 66h. the relation of data area and com / seg pin is as below : read automatically by the display data from the display data area and send to the lcd driver by the hardware. therefore, the display patterns can be changed only by overwritting the contents of the display data area with the software. the relation between lcd display ram and driving method driving method lcd display ram address 40h ~ 46h 50h ~ 56h 50h ~ 66h 1/3 duty com0 com1 com2 1/2 duty com0 com1 - static com0 - - high speed high speed high speed high speed high speed counter counter counter counter counter EM73362 has one high speed counter for resistor to frequency oscillation mode, melody mode and auto load timer mode. the resistor to frequency oscillation (rfo) circuit as show below : p4.0(rx) p4.2(ry) p4.3(rz) p4.1(cs) p18(1..0) mux resistor to frequency oscillator counter f rf p18(3..2) f rf /2 x p5 p3 8-bit counter rate mode p17(1..0) p17(3..2) clock rate gating rate tcb tone address increment bit 0 1 2 3 0 1 2 40h~46h (com0) 50h~56h (com1) 60h~66h (com2) increment seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0
21 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product contr contr contr contr contr ol of high speed counter ol of high speed counter ol of high speed counter ol of high speed counter ol of high speed counter the high speed counter is controlled by the command registers (p17, p18) : p17 3 2 1 0 initial value : 0000 mode rate mode selection of htc mode 0 0 disable htc 0 1 melody mode 1 0 auto load timer mode 1 1 resistor to frequency oscillation mode rate internal pulse rate / counter start request frequency ( hz ) resistor to frequency auto load timer mode / melody oscillation mode mode internal pulse rate 0 0 xin / 2 10 xin / 2 0 0 1 xin / 2 12 xin / 2 2 1 0 xin / 2 14 xin / 2 4 1 1 xin / 2 15 xin / 2 6 p18 3 2 1 0 initial value : 0000 rfip rfin rfip input frequency of rfo rfin selection of rfo pin 0 0 f rf / 2 0 0 normal i/o 0 1 f rf / 4 0 1 p4.0 (rx) for rfo 1 0 f rf / 8 1 0 p4.2 (ry) for rfo 1 1 f rf / 16 1 1 p4.3 (rz) for rfo p3 and p5 are the 8-bit binary counter registers of the htc. p3 is lower nibble register and p5 is higher nibble register. p5 p3 3 2 1 0 3 2 1 0 initial value : 0000 0000 higher nibble register lower nibble register the htc consist of one auto-reload and presetable 8-bit binary counter, 12-bit general counter and clock source selectors. the command register can select the internal clock pulse for the melody, auto load counter and resistor to frequency oscillation modes. the htc increases one at the rising edge of the clock pulses. when the first rising edge occurs by the htc enabled, the htc starts counting.
22 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 8-bit binary counter write the preset value to the registers the value of 8-bit binary counter can be presetted by p3 and p5. the value of registers can be loaded into the 8-bit binary counter when the counter starts counting or occurs overflow. if you write values to the registers before the next overflow occurs, the preset value can be changed. read the count value from the registers the count value of 8-bit binary counter can be read out from p3 and p5. the value is unstable when you read out the value during counting. thus, you must disable the counter before reading out the value. 12-bit general counter (tcb) write the initial value to the registers the initial value can be written into the 12-bit counter registers by using statbl, statbm and statbh instructions. the value of registers can be loaded into the 12-bit binary counter (tcb) and the tcb in creases one when the 8-bit binary counter overflows. read the count value from the registers the count value of 12-bit binary counter can be read out from the counter registers by using ldatbl, ldatbm and ldatbh instructions. 20-bit counter function the 8-bit binary counter is connected to tcb which is one 12-bit general counter and becomes to the 20- bit counter. the tcb increases one when the 8-bit binary counter overflows and generats an overflow interrupt (trgb) when the tcb overflows. in this case, the tcb cannot be used as a 12-bit counter alone. function of high speed counter function of high speed counter function of high speed counter function of high speed counter function of high speed counter the htc has three modes which are rfo mode, melody mode and auto load timer mode. in these mode, the htc loads the initial values from the counter registers (p3, p5) when it is enabled by p17 and it also can be auto-reloaded the initial values when it overflows. the htc is counted by the internal pulse and the value of tcb increases one when 8-bit binary counter overflows. the tcb can generate an overflow interrupt (trgb) when it overflows. the trgb cannot be generated when the htc is in the melody mode or disabled. the htc is disabled when the cpu is reseted or in the stop/idle operation mode. users must enable it by self when the cpu is waked up.
23 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product resistor to frequency oscillation mode in this case, the window gate width interval is from the time base output fall to rise and the value of window gate width setting is the same as the time base interrupt frequency. the time base can be generated a fixed frequency interrupt when the time base interrupt (tbi) is enabled. the content of the htc can be read and initialized by the tbi interrupt service routine. ex. tbi interrupt frequency is xin/2 15 hz (p25=1101b). the pulse rate of rfo is xin/2 15 hz (p17=1111b). the window gate width of rfo is 2 14 /xin sec. program example dseg org 00h rfcon: res 1 : cseg org 00h lbr main ;initial jump org 0ah lbr tbi ;timebase interrupt vector address : ;timebase interrupt service routine tbi: cmp #00h,rfcon b tbi1 std #01h,rfcon ldia #00h ;initial tcb & htc register outa p5 outa p3 statbl statbm statbh b tbiend 00 001 window gate width tbi interrupt service routine n+1 00 01 00 01 n ff enable htc and write data. disable htc and read data. htc input pulse time base program tcb counter 8-bit binary counter 8-bit binary counter overflow
24 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product p5 p3 3 2 1 0 3 2 1 0 initial value : 0000 0000 ( tf ) higher nibble register lower nibble register ** f tone = [ (xin / 2 x ) / (100h - tf) ] / 2, tf = 0 ~ 255 ** example : xin = 32khz, rate = 01, tf = 11110000b = 0f0h. f tone = [ (32k hz / 2 2 ) / (100h - 0f0h) ] / 2 = 256 hz. tbi1: ldia #00h ;disable rfo before reading the counter value outa p17 ina p3 ;store the counter value to ram[00] - ram[04] sta 00h ina p5 sta 01h ldatbl sta 02h ldatbm sta 03h ldatbh sta 04h tbiend: rti ;main program main: std #00h,rfcon ldia #0001b ;p4.0 (rx) output outa p18 ldia #0010b ;enable timebase interrupt exae eicil 0 ldia #1111b ;enable rfo mode, the window gate width of rfo=2 14 /xin sec. outa p17 ldia #1101b ;enable timebase, interrupt frequency : xin / 2 15 hz outa p25 : melody mode the p4.0/ tone and tone pins will output the square wave in the melody mode. when the cpu is not in the melody mode, the p4.0/ tone is high and tone is low. the 8-bit tone frequency register is p5 and p3. the tone frequency will be changed when users output the different data to p3. thus, the data must be output to p5 before p3 when users want to change the 8-bit tone frequency (tf).
25 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product program example : ldia #0fh outa p5 ldia #00h outa p3 outa p18 ldia #0101b ;enable melody mode outa p17 : auto load timer mode in this mode, there are four different internal pulse rates can be selected by p17. the htc loads the initial values by the counter registers (p3, p5) and increases at the rising edges of internal pulse generated by the time base. the value of tcb increases one when the high speed counter overflows and generates an overflow interrupt (trgb) when the tcb overflows. program example : ldia #00h ; initial tcb & htc register statbl statbm statbh outa p5 outa p3 outa p18 ldia #1011b ; auto load timer mode, internal pulse rate : xin/2 6 outa p17 : ldia #00h ; disable timer mode outa p17 ina p3 ; store the counter value to ram[00] - ram[04] sta 00h ina p5 sta 01h ldatbl sta 02h ldatbm sta 03h ldatbh sta 04h
26 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product w w w w w a a a a a tch-dog-timer ( tch-dog-timer ( tch-dog-timer ( tch-dog-timer ( tch-dog-timer ( wdt ) wdt ) wdt ) wdt ) wdt ) watch-dog-timer can help user to detect the malfunction (runaway) of cpu and give system a time up signal every certain time. user can use the time up signal to give system a reset signal when system is fail. this function is available by mask option. if the mask option of wdt is enabled, it will stop counting when cpu is reseted or in the stop operation mode. the basic structure of watch-dog-timer control is composed by a 4-stage binary counter and a control unit. the wdt counter counts for a certain time to check the cpu status, if there is no malfunction happened, the counter will be cleared and counting. otherwise, if there is a malfunction happened, the wdt control will send a wdt signal (low active) to reset cpu. the wdt checking period is assign by p21 (wdt command port). p21 is the control port of watch-dog-timer, and the wdt time up signal is connected to reset . p21 3 2 1 0 initial value : 0000 cwc * * wdt cwc clear watch-dog-timer counter 0 clear counter then return to 1 1 nothing wdt set watch-dog-timer detect time 0 3 x 2 13 /xin = 3 x 2 13 /32k hz = 0.75 sec 1 7 x 2 13 /xin = 7 x 2 13 /32k hz = 1.75 sec program example to enable wdt with 7 x 2 13 /xin detection time. ldia #0001b outa p21 ;set wdt detection time and clear wdt counter : : 0 1 2 3 wdt counter xin / 2 13 wdt control counter clear request wdt command port p21 mask option reset pin
27 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product lo lo lo lo lo w b w b w b w b w b a a a a a tter tter tter tter tter y detect y detect y detect y detect y detect or ( lbd ) or ( lbd ) or ( lbd ) or ( lbd ) or ( lbd ) EM73362 has a built-in low battery detector. this function is disabled when cpu is reseted or in the stop /idle operation mode. user must enable the low battery detector by self when the cpu is waked up. if the low battery detector is enabled, the operating current of whole chip will increase. contr contr contr contr contr ol of lo ol of lo ol of lo ol of lo ol of lo w b w b w b w b w b a a a a a tter tter tter tter tter y detect y detect y detect y detect y detect or or or or or port15 is the control register of low battery detector. p15.1 (low battery detector status) is a read-only bit. when lbe is 1, the low battery detector is enabled. when vdd<1.35 0.05v, slb is 1. p15 ( write port ) p15 ( read port ) initial value : **00 3 2 1 0 3 2 1 0 * * * lbe * * slb * lbe low battery detector control slb status of low battery detector 0 low battery detector disable 0 vdd > 1.25 0.05v 1 low battery detector enable 1 vdd < 1.25 0.05v ( low battery ) bat p15.0 reference voltage + _
28 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product hardware condition in reset state initial value program counter 000h status flag 01h interrupt enable flip-flop ( ei ) 00h mask0 ,1, 2, 3 00h interrupt latch ( il ) 00h p3, 5, 15, 16, 17, 18, 19, 21, 25, 27 00h p4, 6, 7, 8 0fh xin start oscillation resetting function resetting function resetting function resetting function resetting function when cpu in normal working condition and reset pin holds in low level for three instruction cycles at least, then cpu begins to initialize the whole internal states, and when reset pin changes to high level, cpu begins to work in normal condition. the cpu internal state during reset condition is as following table : the reset pin is a hysteresis input pin and it has a pull-up resistor available by mask option. the simplest reset circuit is connect reset pin with a capacitor to v ss and a diode to v dd . reset
29 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product EM73362 port description : EM73362 port description : EM73362 port description : EM73362 port description : EM73362 port description : port port port port port input function input function input function input function input function output function output function output function output function output function note note note note note 0 e input port , wake-up function , external interrupt input 1-- -- 2-- -- 3 -- i high speed counter register low nibble 4 e input port , e output port, p4.0/tone resistor to frequency oscillation 5 -- i high speed counter register high nibble 6 e input port e output port , lcd segment pin 7 e input port e output port , lcd segment pin 8 e input port e output port , lcd segment pin 9-- -- 10 -- -- 11 -- -- 12 -- -- 13 -- -- 14 -- -- 15 i p15.1 ( low battery detector status ) i p15.1 ( low battery detector control ) 16 i stop mode control register 17 i htc control register 18 i htc control register 19 i idle mode control register 20 -- 21 i wdt control register 22 -- 23 -- 24 -- 25 i timebase control register 26 -- 27 i lcd control register 28 i timer a control register 29 -- 30 -- 31 --
30 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product absolute maximum ra absolute maximum ra absolute maximum ra absolute maximum ra absolute maximum ra ting ting ting ting ting items sym. ratings conditions supply voltage v dd -0.5v to 2v input voltage v in -0.5v to v dd + 0.5v output voltage v o -0.5v to v dd + 0.5v power dissipation p d 100mw t opr = 50 c operating temperature t opr 0 c to 50 c storage temperature t stg -55 c to 125 c recommended opera recommended opera recommended opera recommended opera recommended opera ting conditions ting conditions ting conditions ting conditions ting conditions items sym. ratings conditions supply voltage v dd 1.2v to 1.8v fc = 32khz input voltage v ih 0.90 x v dd to v dd v il 0v to 0.10 x v dd dc electrical chara dc electrical chara dc electrical chara dc electrical chara dc electrical chara cteristics ( cteristics ( cteristics ( cteristics ( cteristics ( v v v v v dd dd dd dd dd = 1.5 0.2v = 1.5 0.2v = 1.5 0.2v = 1.5 0.2v = 1.5 0.2v , , , , , v v v v v ss ss ss ss ss = 0v = 0v = 0v = 0v = 0v , , , , , t t t t t opr opr opr opr opr = 25c ) = 25c ) = 25c ) = 25c ) = 25c ) parameters sym. min. typ. max. unit conditions supply current i dd -610 a rc osc. v dd =1.7v, fc=32khz, no load, -58 ax ? tal osc. rfo off, lbd off -48 a rc osc. v dd =1.7v, fc=32khz, idle -36 ax ? tal osc. mode, no load - 0.1 1 av dd =1.7v, stop mode - 80 250 ax ? tal osc. v dd =1.5v, fc=32khz, rfo on -4060 av dd =1.5v, fc=32khz, lbd on low battery detector v lbd 1.20 1.25 1.30 v frequency of rfo f rf1 95 120 140 khz r = 10k ? ,vdd=1.5v f rf2 8.9 10.5 13 khz r = 100k ?, vdd=1.5v f rf3 780 980 1300 hz r = 1m ? ,vdd=1.5v frequency ratio of f rf1 10.1 10.6 11.1 vdd=1.5v, r1=10k ? , r2=100k ? , rfo f rf2 r3=1m ? f rf2 10.1 10.6 11.1 f rf3 hysteresis voltage v hys+ 0.50v dd - 0.75v dd v reset, p0 v hys- 0.20v dd - 0.40v dd v input current i ih -1015 a p0, pull-down, v ih =v dd -15 -10 - a p0, pull-up, v ih =v ss --1 a p0, none output voltage v oh 1.1 - - v push-pull : p4 high current pmos, tone v dd =1.3v, i oh =-500 a 1.1 - - v push-pull : p4 low current pmos, others, v dd =1.3v, i oh =-30 a v ol - - 0.2 v v dd =1.3v, i ol =500 a leakage current i lo --1 a open-drain, v dd =1.7v, v o =1.7v input resistor r in 50 100 200 k ? reset lcd bias voltage v ee 2v dd -0.1 2v dd 2v dd +0.1 v voltage doubler
31 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product parameters sym. min. typ. max. unit conditions com, seg pins vo 1 v ee -0.1 v ee -vio 1 = -5 a output current vo 2 v dd -0.1 v dd v dd +0.1 v io 2 = 5 a vo 3 -v ss v ss +0.1 v io 3 = 5 a frequency stability - 20 - % fc=32k hz, rc osc, r=620k ? , [f(1.5v)-f(1.3v)]/f(1.5v) frequency variation - 20 - % fc=32k hz, v dd =1.5v, rc osc,r=620k ?, [f(typical)-f(worse case)]/f(typical)
32 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product reset pin type type reset_a reset mask option oscillation pin type type osc_a type osc_f xout crystal osc. xin rc osc. (inverter) xin xout input pin type type input_h type input_j : mask option wakeup function mask option : mask option wakeup function mask option special function control input input data i/o pin type type i/o_n type i/o_o : mask option output data latch output data input data path b path a special function output : mask option type i/o_n
33 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product output data input data sel path a path b data latch output special function control input type i/o_n output data mux path a path b special function control output output data latch input data type i/o_n type i/o_x type i/o_y path a :for set and clear bit of port instructions, data goes through path a from output data latch to cpu. path b :for input and test instructions, data from output pin go through path b to cpu and the output data latch will be set to high.
34 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product pad diagram pad diagram pad diagram pad diagram pad diagram chip size : 2140 x 2070 um. pad no. pad no. pad no. pad no. pad no. symbol symbol symbol symbol symbol x x x x x y y y y y 1 seg1 -911.4 752.3 2 seg0 -911.4 632.4 3 com1 -911.4 512.5 4 com0 -911.4 392.0 5 vee -910.5 270.5 6 vb -910.5 148.4 7 va -910.5 27.4 43 44 46 45 47 48 49 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 25 26 27 28 29 30 31 32 33 34 35 36 37 40 38 39 41 42 seg7 seg6 seg5 seg4 seg3 seg2 seg13 seg14 seg12 seg11 seg10 seg9 seg8 p0.3/wakeup3 p0.2(int0)/wakeup2 reset bat xout test p4.3(rz) p4.2(rs) p4.1(cs) p4.0(rx)/tone tone p8.0/seg15 p8.2/seg17 p8.3/seg18 p7.0/seg19 p7.1/seg20 p7.2/seg21 p7.3/seg22 p6.1/seg24 p6.0/seg23 p6.2/seg25 p8.1/seg16 p6.3/seg26 seg0 com1 com0 vee vb va vss xin (0,0) y x EM73362 24 12 1 com2 p0.1/wakeup1 p0.0(int1)/wakeup0 vdd seg1
35 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product pad no. pad no. pad no. pad no. pad no. symbol symbol symbol symbol symbol x x x x x y y y y y 8 vss -896.4 -132.1 9 xin -911.4 -263.9 10 xout -911.4 -636.1 11 vdd -892.4 -857.5 12 bat -705.0 -874.1 13 reset -583.0 -874.1 14 p0.0(int1)/wakeup0 -463.1 -874.1 15 p0.1/wakeup1 -338.5 -874.1 16 p0.2(int0)/wakeup2 -213.8 -874.1 17 po.3/wakeup3 -89.2 -874.1 18 tone 47.3 -877.4 19 p4.0(rx)/tone 168.8 -877.4 20 p4.1(cs) 290.4 -877.4 21 p4.2(rs) 411.9 -877.4 22 p4.3(rz) 533.5 -877.4 23 test 655.6 -874.1 24 com2 907.9 -772.2 25 p6.3/seg26 907.1 -637.8 26 p6.2/seg25 907.1 -516.2 27 p6.1/seg24 907.1 -394.7 28 p6.0/seg23 907.1 -273.1 29 p7.3/seg22 907.1 -151.6 30 p7.2/seg21 907.1 -30.0 31 p7.1/seg20 907.1 91.5 32 p7.0/seg19 907.1 213.1 33 p8.3/seg18 907.1 334.6 34 p8.2/seg17 907.1 456.2 35 p8.1/seg16 907.1 577.7 36 p8.0/seg15 907.1 699.3 37 seg14 692.3 874.7 38 seg13 572.4 874.7 39 seg12 452.5 874.7 40 seg11 332.6 874.7 41 seg10 212.7 874.7 42 seg9 92.8 874.7 43 seg8 -27.1 874.7 44 seg7 -147.0 874.7 45 seg6 -266.9 874.7 46 seg5 -386.8 874.7 47 seg4 -506.7 874.7 48 seg3 -626.6 874.7 49 seg2 -746.5 874.7 unit : m for pcb layout, ic substrate must be floated or connected to vss.
36 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product instruction table instruction table instruction table instruction table instruction table (1) data transfer (1) data transfer (1) data transfer (1) data transfer (1) data transfer mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s lda x 0110 1010 xxxx xxxx acc ram[x] 2 2 - z 1 ldam 0101 1010 acc ram[hl] 1 1 - z 1 ldax 0110 0101 acc rom[dp] l 12-z1 ldaxi 0110 0111 acc rom[dp] h ,dp+1 1 2 - z 1 ldh #k 1001 kkkk hr k11--1 ldhl x 0100 1110 xxxx xx00 lr ram[x],hr ram[x+1] 2 2 - - 1 ldia #k 1101 kkkk acc k11-z1 ldl #k 1000 kkkk lr k11--1 sta x 0110 1001 xxxx xxxx ram[x] acc 2 2 - - 1 stam 0101 1001 ram[hl] acc 1 1 - - 1 stamd 0111 1101 ram[hl] acc, lr-1 1 1 - z c stami 0111 1111 ram[hl] acc, lr+1 1 1 - z c' std #k,y 0100 1000 kkkk yyyy ram[y] k22--1 stdmi #k 1010 kkkk ram[hl] k, lr+1 1 1 - z c' tha 0111 0110 acc hr 1 1 - z 1 tla 0111 0100 acc lr 1 1 - z 1 (2) rotate (2) rotate (2) rotate (2) rotate (2) rotate mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s rlca 0101 0000 cf acc 11czc' rrca 0101 0001 cf acc 11czc' ( 3) arithmetic operation 3) arithmetic operation 3) arithmetic operation 3) arithmetic operation 3) arithmetic operation mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s adcam 0111 0000 acc acc + ram[hl] + cf 1 1 c z c' add #k,y 0100 1001 kkkk yyyy ram[y] ram[y] +k 2 2 - z c' adda #k 0110 1110 0101 kkkk acc acc+k 2 2 - z c' addam 0111 0001 acc acc + ram[hl] 1 1 - z c' addh #k 0110 1110 1001 kkkk hr hr+k 2 2 - z c' addl #k 0110 1110 0001 kkkk lr lr+k 2 2 - z c' addm #k 0110 1110 1101 kkkk ram[hl] ram[hl] +k 2 2 - z c' deca 0101 1100 acc acc-1 1 1 - z c decl 0111 1100 lr lr-1 1 1 - z c decm 0101 1101 ram[hl] ram[hl]-1 1 1 - z c inca 0101 1110 acc acc + 1 1 1 - z c'
37 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product incl 0111 1110 lr lr + 1 1 1 - z c' incm 0101 1111 ram[hl] ram[hl]+1 1 1 - z c' suba #k 0110 1110 0111 kkkk acc k-acc 2 2 - z c sbcam 0111 0010 acc ram[hll - acc - cf' 1 1 c z c subm #k 0110 1110 1111 kkkk ram[hl] k - ram[hl] 2 2 - z c ( ( ( ( ( 4) logical operation 4) logical operation 4) logical operation 4) logical operation 4) logical operation mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s anda #k 0110 1110 0110 kkkk acc acc&k 2 2 - z z' andam 0111 1011 acc acc & ram[hl] 1 1 - z z' andm #k 0110 1110 1110 kkkk ram[hl] ram[hl]&k 2 2 - z z' ora #k 0110 1110 0100 kkkk acc acc k 2 2 - z z' oram 0111 1000 acc acc ram[hl] 1 1 - z z' orm #k 0110 1110 1100 kkkk ram[hl] ram[hl] k 2 2 - z z' xoram 0111 1001 acc acc^ram[hl] 1 1 - z z' (5) exchange (5) exchange (5) exchange (5) exchange (5) exchange mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s exa x 0110 1000 xxxx xxxx acc ? ram[x] 2 2 - z 1 exah 0110 0110 acc ? hr 1 2 - z 1 exal 0110 0100 acc ? lr 1 2 - z 1 exam 0101 1000 acc ? ram[hl] 1 1 - z 1 exhl x 0100 1100 xxxx xx00 lr ? ram[x], hr ? ram[x+1] 2 2 - - 1 (6) branch (6) branch (6) branch (6) branch (6) branch mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s sbr a 00aa aaaa if sf=1 then pc pc 11-6 .a 5-0 11--1 else null lbr a 1100 aaaa aaaa aaaa if sf= 1 then pc a else null 2 2 - - 1 (7) compare (7) compare (7) compare (7) compare (7) compare mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s cmp #k,y 0100 1011 kkkk yyyy k-ram[y] 2 2 c z z' cmpa x 0110 1011 xxxx xxxx ram[x]-acc 2 2 c z z' cmpam 0111 0011 ram[hl] - acc 1 1 c z z' cmph #k 0110 1110 1011 kkkk k - hr 2 2 - z c cmpia #k 1011 kkkk k - acc 1 1 c z z' cmpl #k 0110 1110 0011 kkkk k-lr 2 2 - z c - - - - - -
38 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product (8) bit manipulation (8) bit manipulation (8) bit manipulation (8) bit manipulation (8) bit manipulation mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s clm b 1111 00bb ram[hl] b 011--1 clp p,b 0110 1101 11bb pppp port[p] b 022--1 clpl 0110 0000 port[lr 3-2 +4] lr 1-0 012--1 clr y,b 0110 1100 11bb yyyy ram[y] b 022--1 sem b 1111 01bb ram[hl] b 111--1 sep p,b 0110 1101 01bb pppp port[p] b 122--1 sepl 0110 0010 port[lr 3-2 +4] lr l-0 112 --1 set y,b 0110 1100 01bb yyyy ram[y] b 122--1 tf y,b 0110 1100 00bb yyyy sf ram[y] b '22--* tfa b 1111 10bb sf acc b '11--* tfm b 1111 11bb sf ram[hl] b '11--* tfp p,b 0110 1101 00bb pppp sf port[p] b '22--* tfpl 0110 0001 sf port[lr 3-2 +4] lr 1-0 '12--* tt y,b 0110 1100 10bb yyyy sf ram[y] b 22--* ttp p,b 0110 1101 10bb pppp sf port[p] b 22--* (9) subroutine (9) subroutine (9) subroutine (9) subroutine (9) subroutine mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s lcall a 0100 0aaa aaaa aaaa stack[sp] pc, 2 2 - - - sp sp -1, pc a scall a 1110 nnnn stack[sp] pc, 1 2 - - - sp sp - 1, pc a,a = 8n + 6 (n =115 ),0086h (n = 0) ret 0100 1111 sp sp + 1, pc stack[sp] 1 2 - - - (10) input/output (10) input/output (10) input/output (10) input/output (10) input/output mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s ina p 0110 1111 0100 pppp acc port[p] 2 2 - z z' inm p 0110 1111 1100 pppp ram[hl] port[p] 2 2 - - z' out #k,p 0100 1010 kkkk pppp port[p] k22--1 outa p 0110 1111 000p pppp port[p] acc 2 2 - - 1 outm p 0110 1111 100p pppp port[p] ram[hl] 2 2 - - 1 (11) flag manipulation (11) flag manipulation (11) flag manipulation (11) flag manipulation (11) flag manipulation mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s cgf 0101 0111 gf 011--1 sgf 0101 0101 gf 111--1
39 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product tfcfc 0101 0011 sf cf', cf 0110-* tgs 0101 0100 sf gf 1 1 - - * ttcfs 0101 0010 sf cf, cf 1111-* tzs 0101 1011 sf zf 1 1 - - * (12) interrupt control (12) interrupt control (12) interrupt control (12) interrupt control (12) interrupt control mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s cil r 0110 0011 11rr rrrr il il & r 2 2 - - 1 dicil r 0110 0011 10rr rrrr eif 0,il il&r 2 2 - - 1 eicil r 0110 0011 01rr rrrr eif 1,il il&r 2 2 - - 1 exae 0111 0101 mask ? acc 1 1 - - 1 rti 0100 1101 sp sp+1,flag.pc 1 2 * * * stack[sp],eif 1 (13) cpu control (13) cpu control (13) cpu control (13) cpu control (13) cpu control mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s nop 0101 0110 no operation 1 1 - - - (14) timer/counter & data pointer & stack pointer control (14) timer/counter & data pointer & stack pointer control (14) timer/counter & data pointer & stack pointer control (14) timer/counter & data pointer & stack pointer control (14) timer/counter & data pointer & stack pointer control mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) mnemonic object code ( binary ) operation description operation description operation description operation description operation description byte byte byte byte byte cycle cycle cycle cycle cycle flag flag flag flag flag c c c c c z z z z z s s s s s ldadpl 0110 1010 1111 1100 acc [dp] l 22-z1 ldadpm 0110 1010 1111 1101 acc [dp] m 22-z1 ldadph 0110 1010 1111 1110 acc [dp] h 22-z1 ldasp 0110 1010 1111 1111 acc sp 2 2 - z 1 ldatal 0110 1010 1111 0100 acc [ta] l 22-z1 ldatam 0110 1010 1111 0101 acc [ta] m 22-z1 ldatah 0110 1010 1111 0110 acc [ta] h 22 -z1 ldatbl 0110 1010 1111 1000 acc [tb] l 22-z1 ldatbm 0110 1010 1111 1001 acc [tb] m 22-z1 ldatbh 0110 1010 1111 1010 acc [tb] h 22-z1 stadpl 0110 1001 1111 1100 [dp] l acc 2 2 - - 1 stadpm 0110 1001 1111 1101 [dp] m acc 2 2 - - 1 stadph 0110 1001 1111 1110 [dp] h acc 2 2 - - 1 stasp 0110 1001 1111 1111 sp acc 2 2 - - 1 statal 0110 1001 1111 0100 [ta] l acc 2 2 - - 1 statam 0110 1001 1111 0101 [ta] m acc 2 2 - - 1 statah 0110 1001 1111 0110 [ta] h acc 2 2 - - 1 statbl 0110 1001 1111 1000 [ tb] l acc 2 2 - - 1 statbm 0110 1001 1111 1001 [tb] m acc 2 2 - - 1 statbh 0110 1001 1111 1010 [tb] h acc 2 2 - - 1
40 * this specification are subject to be changed without notice. 10.8.2001 EM73362 EM73362 EM73362 EM73362 EM73362 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product 4-bit micro-controller for lcd product hr h register lr l register pc program counter dp data pointer sp stack pointer stack[sp] stack specified by sp a cc accumulator flag all flags cf carry flag zf zero flag sf status flag gf general flag ei enable interrupt register il interrupt latch mask interrupt mask port[p] port ( address : p ) ? timer/counter a ? timer/counter b ram[hl] data memory (address : hl ) ram[x] data memory (address : x ) rom[dp] l low 4-bit of program memory rom[dp] h high 4-bit of program memory [dp] l low 4-bit of data pointer register [dp] m middle 4-bit of data pointer register [dp] h high 4-bit of data pointer register [ta] l ([tb] l ) low 4-bit of timer/counter a (timer/counter b) register [ta] m ([tb] m ) middle 4-bit of timer/counter a [ta] h ([tb] h ) high 4-bit of timer/counter a (timer/counter b) register (timer/counter b) register transfer ? exchange + addition - substraction & logic and logic or ^ logic xor ' inverse operation . concatenation #k 4-bit immediate data x 8-bit ram address y 4-bit zero-page address p 4-bit or 5-bit port address b bit address r 6-bit interrupt latch pc 11-6 bit 11 to 6 of program counter lr 1 -0 contents of bit assigned by bit a 5-0 bit 5 to 0 of destination address for 1 to 0 of lr branch instruction lr 3-2 bit 3 to 2 of lr - - **** symbol description **** symbol description **** symbol description **** symbol description **** symbol description symbol symbol symbol symbol symbol description description description description description symbol symbol symbol symbol symbol description description description description description

▲Up To Search▲

Price & Availability of EM73362

	To Download EM73362 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .